![]() Choosing a logic gate When unsure which logic gate to use, try building a table like the one down below but with just one row of outputs. When an XOR gate is combined in this way, its output is on when an odd number of inputs is on. For these gates, the order in which the inputs are combined doesn't matter. Stacking inputs The AND, OR, and XOR gates can each be used in arrays to perform their operation on more than two inputs, by combining two inputs at a time, then combining the results with each other and/or other inputs. Swapping the inputs of the IMPLIES gate will affect its output, and the NOT gate has only one input. ![]() Swapping inputs For most of these gates, A and B can be swapped without changing the output. Data sheets for discrete JFETs typically fix D, G, and S, so there must be some asymmetry.The output of each logic circuit reflects the state of its inputs at all times (though possibly with some delay incurred by the circuit). Integrated JFETs (if you have any as special input devices for a CMOS process) are typically symmetric. Power MOSFETs are non symmetric due to their voltage blocking capability on the drain side and vertical construction (source and gate on top of the chip, drain on the back). You may tie source to bulk in the package and get a non symmetric three terminal device. Typically they are symmetric.ĭiscrete MOSFETs: If you have four terminals and low voltage, they may be symmetric. They may have lower noise because the channel is buried somewhat in the substrate, away from the gate oxide Si interface. Connecting gate and source may yield a nice 'conststant' current source, because you have one branch of MOS output characteristics, which is flat (nearly not depending on drain voltage) in saturation. MOS devices with Vt<0 (depletion mode transistors) have been used as inverter load in NMOS enhancement depletion logic in the last century. Integrated DMOS are not symmetric do to space consuming high voltage capability on the drain side. You can make them symmetric, however, if you need. Integrated high voltage MOS are typically not symmetric, because the high voltage capability is added only to the drain side (adds series resistance, not liked on source side, and costs floor space). Integrated low voltage MOS are typically symmetrical, source and drain determined only by biasing. I've never done that myself if you achieve interesting results I will be eager to hear them. First use a tech file (not a discrete mosfet they might not have symmetry), then simulate it with proper biasing for both cases. I do not know why would anyone do that, it might work as a startup circuit.īut here is a suggestion I believe if you bias your transistors properly you can see that the MOSFETs are symmetrical. They will be conducting current even if their gate is connected to their source. Regarding your question I think the same as moottii but I must add that there are transistors that have negative threshold voltage. But there are specialized devices like LDMOS or some other. In layout they look mostly symmetrical and process vendor actually doesn't care which side is drain and which side is source. ![]() So other than switching applications it is better to use them as they are, in simulations of course. However I do not think that they model them that way. Firstly, in many modern technologies you can choose which side is drain and which side is source with just biasing.
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